1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly, to a dynamic random access memory (DRAM) device and a method of manufacturing the same.
2. Description of the Related Art
As the technology for manufacturing semiconductor devices has progressed and become more developed, because of increasing demands for products that utilize memory devices, there has been a demand to provide larger capacity memory devices. To help meet this demand, the integration density of a DRAM device whose memory cell is composed of one capacitor and one transistor has been remarkably improved.
Accordingly, as the integration density of a semiconductor device increases, a size of a contact hole connecting one element to another element or one film to another film is reduced, while a thickness of an interlayer dielectric film is augmented. Thus, an aspect ratio of the contact hole, i.e., a ratio of the diameter of the contact hole relative to the length of the contact hole, increases so that an alignment margin for forming the contact hole decreases during a photolithographic process. As a result, the formation of a minute contact hole may become very difficult through conventional methods of forming contact holes.
For DRAM devices in particular, a process for introducing a landing pad is widely used to reduce the aspect ratio of the contact hole. Also, a self-aligned contact structure is commonly employed for a pattern having a feature size of below 0.1 mm to settle a short-circuit problem caused by a reduction in the alignment margin.
FIGS. 1A to 1C are diagrams of cross-sectional views illustrating a conventional method of manufacturing a DRAM device having a self-aligned contact structure.
Referring to FIG. 1A, metal oxide semiconductor (MOS) transistors (not shown) respectively having gate electrodes and source/drain regions are formed on a semiconductor substrate 10. Each gate electrode includes a gate insulating film, a gate capping film composed of silicon nitride, and a gate sidewall spacer composed of silicon nitride.
After a first interlayer dielectric film 12, composed of silicon oxide, is formed on the substrate 10, where the MOS transistors are formed, the first interlayer dielectric film 12 is planarized by a chemical mechanical polishing (CMP) process or an etch-back process. Then, the first interlayer dielectric film 12 is etched under an etching condition having a high etching selectivity relative to silicon nitride, thereby forming contact holes 13 and exposing the source/drain regions. At this time, the contact holes 13 are self-aligned relative to the gate electrodes, respectively.
After a doped polysilicon film (not shown) is formed on the first interlayer dielectric film 12 to fill up the contact holes 13, the doped polysilicon film is etched by a CMP process or an etch-back process to form pad electrodes 14 contacting with the source/drain regions of the MOS transistors.
Next, a second interlayer dielectric film 16, composed of silicon oxides is formed on the first interlayer dielectric film 12 and the pad electrodes 14. The second interlayer dielectric film 16 has a thickness of about 1000 to about 3,000 Å. The second interlayer dielectric film 16 is planarized by a CMP process or an etch-back process. With a typical photolithographic process, the second interlayer dielectric film 16 is partially etched to form bit line contact holes (not shown) exposing the pad electrodes 14. The bit line contact holes are then filled using a conductive material to form bit line contact plugs (not shown) therein. The bit line contact plugs are connected to the pad electrodes positioned on the source/drain regions.
A conductive film (not shown), e.g., a tungsten film, is formed on the second interlayer dielectric film 16 and the bit line contact plugs. The conductive film has a thickness of about 400 to about 800 Å.
A bit line mask layer (not shown) composed of silicon nitride is the formed on the conductive film. The bit line mask layer has a relatively thick thickness of about 3000 Å. The bit line mask layer and the conductive film are successively etched by a photolithographic process to form bit lines 22 composed of bit line mask layer patterns 20 and conductive layer patterns 18. The bit lines 22 are connected to the bit line contact plugs, respectively.
Referring to FIG. 1B, after a silicon nitride film is formed on the bit lines 22 and the second interlayer dielectric film 16, the silicon nitride film is anisotropically etched to form bit line spacers 24 on sidewalls of the bit lines 22, respectively.
Referring to FIG. 1C, a third interlayer dielectric film 26, composed of boro-phosphor silicate glass (BPSG), undoped silicate glass (USG), high density plasma (HDP) oxide, or chemical vapor deposited (CVD) oxide, is formed on a surface of the resultant structure. Then, the third interlayer dielectric film 26 is planarized by a CMP process or an etch-back process.
On the third interlayer dielectric film 26, photoresist patterns (not shown) that define storage node contact hole regions are formed by a photolithographic process. At this time, each photoresist pattern has an open region that is wider than the interval between adjacent bit lines 22. Thus, the bit line mask layer pattern 20 positioned at an edge portion of the bit line 22 and the bit line spacer 24 on the sidewall of the bit line 22 are exposed.
Using the photoresist patterns as etching masks, the third interlayer dielectric film 26 and the second interlayer dielectric film 16 are selectively etched with an etching gas having a high etching selectivity relative to the bit line spacers 24, which are composed of silicon nitride. This etching process forms storage node contact holes 28 that are self-aligned to the bit lines 22. The storage node contact holes 28 expose the pad electrodes 14 between the bit lines 22, i.e., the pad electrodes 14 formed on the source regions.
After removing the photoresist patterns, storage node contact plugs (not shown), composed of a conductive material, such as doped polysilicon, are formed in the storage node contact holes 28, respectively.
According to the above-described conventional method, because the thickness of the bit line mask layer pattern 20 composed of silicon nitride should be augmented so as to ensure a margin for the self-aligned contact etching process, a height of the bit line 22 should be also increased. However, when a design rule for a pattern is reduced to below 0.1 mm, the interval between the bit lines 22 is also reduced, thereby increasing the aspect ratio of the bit line 22. Furthermore, when the third interlayer dielectric film 26 is formed on the bit lines 22 having the bit line spacers 24, the interval between the bit lines 22 may become even more narrow leading to increases in the aspect ratios of the bit lines 22. As a result, the gap between the bit lines 22 may be not completely filled with the third interlayer dielectric film 26, thereby causing voids in the third interlayer dielectric film 26.
When voids are formed in the third interlayer dielectric film 26 as described above, they can further expand during subsequent cleaning processes. Now, when the polysilicon film for the storage node contact plug is formed, polysilicon may permeate into the expanded voids creating a bridge connection between adjacent storage node contact plugs. If the thickness of the bit line mask layer is reduced to settle this problem, bit line notching may occur due to a low etching selectivity between the photoresist and the silicon nitride.
Meanwhile, when the self-aligned contact etching process is performed for forming the storage node contact holes 28, the bit line mask layer patterns 20 and the bit line spacers 24, which protect the underlying bit lines 22, are etched because of the small shoulder margins of the bit lines 22. This additional etching can generate a short-circuit between the bit line 22 and the storage node contact plug.
The bit lines are generally used with wiring to detect the existence of charges stored on the memory cells of DRAM devices, and they are also connected to sense amplifiers in a peripheral circuit region. Variations in the bit line voltage are detected by detecting the charges stored on the memory cells. These voltage variations are augmented as the storage capacitance of the memory cell increases or the bit line loading capacitance decreases. Because the decrease of the bit line loading capacitance improves the sensitivity of the sense amplifier, it is preferable to reduce this capacitance, especially when considering the additional improvements in reliability and response speed.
In the above-described conventional method, parasitic capacitance, i.e. the bit line loading capacitance between the bit line and the storage node contact plug or between the bit lines, may be increase because the bit line spacers 24, which are composed of silicon nitride having a high dielectric constants, are formed on the sidewalls of the bit lines 22 to form the self-aligned contact structure. Additionally, the bit line loading capacitance generally increases as the thickness of the bit line spacers 24 decrease. Thus, when the thickness of the bit line spacer 24 is greatly reduced in accordance with the above-mentioned principles, the bit line loading capacitance is largely increased. Though the number of the bit lines 22 positioned in the cell array region could be reduced to help solve the above-mentioned problems, the number of effective chips formed on a wafer may decrease in accordance with the decrease of the bit lines 22 in the cell array region.
U.S. Pat. No. 6,458,692 and Japanese Laid Open Patent Publication No. 2001-217405 disclose methods of forming contacts using spacers composed of silicon oxide having a low dielectric constant. The spacers are formed on the sidewalls of bit lines, thereby reducing a bit line loading capacitance. However, in the above methods, a reduction in the thickness of the bit line mask layer may limit the gap-fill margin of an interlayer dielectric film or decrease the shoulder margin of a bit line during an etching process for a self-aligned contact. As a result, an electrical short-circuit may be generated between the bit line and a storage node contact plug.